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ADuM5401W/ADuM5402W/ADuM5403W
available at V ISO .
I ISO (D)n is the dynamic load current drawn from V ISO by an input
or output channel, as shown in Figure 21 and Figure 22.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of I DD1 and I ISO (LOAD) .
POWER CONSIDERATIONS
The ADuM5401W/ADuM5402W/ADuM5403W power input,
data input channels on the primary side, and data channels on
the secondary side are all protected from premature operation
by UVLO circuitry. Below the minimum operating voltage, the
power converter holds its oscillator inactive and all input channel
drivers and refresh circuits are idle. Outputs remain in a high
impedance state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to V DD1 , the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because
no data comes from the secondary side inputs until secondary
power is established.
The primary side oscillator also begins to operate, transferring
power to the secondary power circuits. The secondary V ISO
voltage is below its UVLO limit at this point; the regulation
control signal from the secondary is not being generated. The
primary side power oscillator is allowed to free run in this
circumstance, supplying the maximum amount of power to the
secondary side, until the secondary voltage rises to its regulation
setpoint. This creates a large inrush current transient at V DD1 .
When the regulation point is reached, the regulation control
circuit produces the regulation control signal that modulates
the oscillator on the primary side. The V DD1 current is reduced
and is then proportional to the load current. The inrush current
is less than the short-circuit current shown in Figure 12. The
duration of the inrush current depends on the V ISO loading
conditions and the current available at the V DD1 pin.
As the secondary side converter begins to accept power from
the primary, the V ISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the correspond-
ing primary side input. It can take up to 1 μs after the secondary
side is initialized for the state of the output to correlate with the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Data Sheet
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care with the design to allow the
converter sufficient time to stabilize before valid data is required.
When power is removed from V DD1 , the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge. The
outputs on the secondary side hold the last state that they received
from the primary side. Either the UVLO level is reached and the
outputs are placed in their high impedance state, or the outputs
detect a lack of activity from the primary side inputs and the
outputs are set to their default low value before the secondary
power reaches UVLO.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insula-
tion degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM5401W/ADuM5402W/
ADuM5403W.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calcu-
lation of the time to failure at the working voltage of interest.
The values shown in Table 20 summarize the peak voltages for
50 years of service life in several operating conditions. In many
cases, the working voltage approved by agency testing is higher
than the 50-year service life voltage. Operation at working
voltages higher than the service life voltage listed leads to
premature insulation failure.
The insulation lifetime of the ADuM5401W/ADuM5402W/
ADuM5403W depends on the voltage waveform type imposed
across the isolation barrier. The i Coupler insulation structure
degrades at different rates, depending on whether the waveform is
bipolar ac, unipolar ac, or dc. Figure 28, Figure 29, and Figure 30
illustrate these different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines the
maximum working voltage recommended by Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms to
either the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 29 or Figure 30
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 20.
Rev. D | Page 22 of 24
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